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- Path: comma.rhein.de!serpens!not-for-mail
- From: mlelstv@serpens.rhein.de (Michael van Elst)
- Newsgroups: comp.sys.amiga.programmer
- Subject: Re: CHIP RAM speed test resul
- Date: 5 Apr 1996 08:41:57 +0200
- Organization: dis-
- Message-ID: <4k2fbl$lag@serpens.rhein.de>
- References: <4j6jv0$1im@serpens.rhein.de> <5827.6659T112T770@mbox.vol.it> <1996Apr2.234528.8971@scala.scala.com> <4k1kk3$i2q@sunsystem5.informatik.tu-muenchen.de>
- NNTP-Posting-Host: serpens.rhein.de
-
- fischerj@Informatik.TU-Muenchen.DE (Juergen "Rally" Fischer) writes:
-
- >ok, so why my 020 needs _12_ cycles , i.e. _846_ ns (!!!!) to load a
- >byte/.w/.l from chipmem ?
-
- Maybe chip-bus contention ?
-
- >why AGA got the curious quality that _any_ kind of chipmem acess is
- >just 2 times slower than it is in fastmem ?
-
- This obviously depends on the speed of your fastmem.
-
- >that's unlogic, because any acess should be delayed by a fix amount
- >of time. but: load 6 -> 12 cycles (difference: 6), store 4 -> 8 cycles
- >(difference: 4).
-
- No. Writes are usually faster because a write cycle can complete while
- the CPU continues with internal operation. A read must complete because
- the CPU needs the data fetched.
-
- >: perfectly aligned with the chip bus timing, or you would need a FIFO
- >: device to store the fetched data for when CPU could take it.
-
- >again, beeing no expert at all, I can't stand the feeling that this FIFO
- >would be just another $0.2 TTLs. again, what about walker ?
-
- No, it would be more than $0.2 (and very few TTL parts cost $0.2
- anyway).
-
- >I see there's no way for a compatible AGA+ _now_, but adding some TTLs
- >should really not be that problem for a company.
- >Am I missing something ?
-
- Yes. "Adding some TTLs" needs lots of board space. And that is a price
- issue.
-
-
-
- --
- Michael van Elst
-
- Internet: mlelstv@serpens.rhein.de
- "A potential Snark may lurk in every tree."
-